1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device comprising a low-dielectric-constant interlayer insulating film having a dual damascene multi-layer wiring structure, and particularly a method for manufacturing a semiconductor device having a dual damascene wiring structure excellent in shape.
2. Description of the Related Art
An electric signal delay due to the time constant of wiring has became a serious problem with the miniaturization and higher integration of semiconductor devices. Therefore, instead of aluminum (Al) alloy wiring, copper (Cu) wiring having low electric resistance has been introduced into an electrically conductive layer used in a multi-layer wiring structure.
Unlike metal materials such as Al and the like used for conventional multi-layer wiring structures, Cu has a difficulty in patterning by dry etching, and thus a damascene method is generally applied to a Cu multilayer wiring structure, in which a Cu film is buried in a wring groove formed in an insulating film to form a wiring pattern.
Particularly, the dual damascene method disclosed in Japanese Unexamined Patent Application Publication No. 10-143914 comprises forming connecting holes and wiring grooves and then simultaneously burying Cu in the holes and grooves, and this method attracts attention because it is effective in decreasing the number of the steps.
In a high-integrated semiconductor device, an increase in inter-wiring capacity decreases the operation speed of the semiconductor device, and thus micro multi-layer wiring using a low-dielectric constant film as an interlayer insulating film is indispensable for suppressing an increase in inter-wiring capacity.
In addition to fluorine-containing silicon oxide (FSG) having a relative dielectric constant of about 3.5 and conventionally proven by actual use, low dielectric constant films having a relative dielectric constant of about 2.7 and made of organic silicone polymers such as polyaryl ether (PAE), inorganic materials such as hydrogen silsequioxane (HSQ), methyl silsesquioxane (MSQ), and the like can be used as materials for a low dielectric constant interlayer insulating film. Furthermore, attempts have recently been made to make these materials porous and use as low dielectric constant materials having a relative dielectric constant of about 2.2.
When the dual damascene method is applied to the low dielectric constant interlayer insulating film, the technical restrictions described below must be resolved.
First, the low dielectric constant film has a composition close to the composition of a resist used for patterning, and thus the low dielectric constant film is also easily damaged in a resist removing process. Specifically, inhibition of damage to the low dielectric constant film is indispensable in peeling the resist after etching using a resist mask and in regenerating the resist when the treated resist pattern does not satisfy product specifications.
Second, attention must be paid to the application of the dual damascene method to a borderless structure with no margin between wiring and connecting holes.
Multi-layer wiring after the 0.18 μm generation of micro semiconductor devices is based on the major premise that a process adaptable to a borderless structure is used. Therefore, it is important to use a process causing little variation in via resistance due to misalignment even when a wiring groove and a connecting hole are simultaneously formed in an interlayer insulating film including a low dielectric constant film by the dual damascene method.
Third, in order to form the wiring grooves with high controllability of depth, an anti-etching film is preferably disposed near the bottoms of the wiring grooves. However, when the anti-etching film having a relatively high relative dielectric constant is disposed in an interlayer insulating film, the interlayer capacity is undesirably increased.
Therefore, a dual damascene process capable of controlling the formation of the wiring grooves while suppressing an increase in capacity is required for a low dielectric constant interlayer film structure.
An example of a dual damascene process capable of resolving the above-described technical restrictions is the technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-150519 or 2001-44189.
An example of application of the dual damascene process to a low dielectric constant interlayer film disclosed in Japanese Unexamined Patent Application Publication No. 2001-44189 will be described below with reference to FIGS. 11 to 13. FIGS. 11A and 11B, FIGS. 12C to 12E, and FIGS. 13F and 13G are sectional views showing respective steps for forming a dual damascene structure by the method disclosed in Japanese Unexamined Patent Application Publication No. 2001-44189.
First, as shown in FIG. 11A, a laminated film including an organic insulating film 52 and a silicon oxide (SiO2) film 53 is deposited as an inter-wring insulating film on an underlying insulating film 51 deposited on a substrate not shown in the drawing, and then copper (Cu) film buried wiring 54 is formed in the inter-wiring insulating film.
Then, a silicon carbide (SiC) film 55 functioning as an antioxidative layer for the Cu film, a carbon-containing silicon oxide (SiOC) film 56 such as a methyl silsesquioxane (MSQ) film, and a polyaryl ether (PAE) film 57 as an organic insulating film are successively deposited on the Cu buried wiring 54.
Then, a silicon oxide (SiO2) film 58 functioning as a first mask forming layer and a silicon nitride (SiN) film 59 functioning as a second mask forming layer are successively deposited. Furthermore, a resist mask 60 having a wiring groove pattern is formed on the SiN film 59.
Next, as shown in FIG. 11B, the SiN film 59 is etched by a dry etching method using the resist mask 60 to form a second mask 59′ (SiN film 59) having the wiring groove pattern, and then the resist mask 60 is removed.
Then, a resist mask 61 having a connecting hole pattern is formed on the second mask 59′ and the SiO2 film 58 so that at least a portion of the resist pattern for the connecting hole pattern overlaps with the second mask 59′ (SiN film 59) having the wiring groove pattern.
As shown in FIG. 12C, the second mask 59′ comprising the SiN film and the SiO2 film 58 functioning as the first mask forming layer are etched by a dry etching method using the resist mask 61 having the connecting hole pattern to form apertures, and then the PAE film 57 is etched to form connecting holes 62 in which the SiOC film 56 is exposed. The resist mask 61 can be removed at the same time as etching of the PAE film 57.
Although the resist mask 61 is gradually thinned during the formation of the holes in the PAW film 57, the connecting holes 62 having a good open shape can be formed through a first mask 58′ because of the presence of the first mask 58′ comprising the SiO2 film 58.
Next, as shown in FIG. 12D, the SiOC film 56 is further etched to dig down the connecting holes 62 to the SiC film 55 and form connecting holes 63. At the same time as the formation of the connecting holes 63, the SiO2 film 58 constituting the first mask 58′ and remaining in the wiring groove formation region is etched through the second mask 59′ (SiN film 59) having the wiring groove pattern to form a wiring groove pattern 64.
As shown in FIG. 12E, the PAE film 57 remaining at the bottom of the wiring groove pattern 64 is etched to form wiring grooves 66, and the SiC film 55 remaining at the bottoms of the connecting holes 63 is etched to communicate the connecting holes 63 with the Cu buried wiring 54, thereby completing the predetermined dual damascene process for forming the connecting holes 65 and the wiring grooves 66.
The second mask 59′ (SiN film 59) remaining out of the wiring groove region is removed in the process for etching the SiC film 55 remaining at the bottoms of the connecting holes 63.
Then, the extraneous matters remaining after etching on the side walls of the connecting holes 65 and the wiring grooves 66 are removed by a post-treatment with a chemical and RF sputtering to normalize Cu affected layers at the bottoms of the connecting holes 65. Then, as shown in FIG. 13F, a Ta film 67 is deposited as a barrier metal by sputtering, and a Cu film 68 is deposited by an electrolytic plating or sputtering method to bury an electrically conductive film in the connecting holes 65 and the wiring grooves 66.
Next, as shown in FIG. 13G, portions of the deposited Ta film 67 and Cu film 68, which are unnecessary for the wiring pattern, are removed by a chemical mechanical polishing (CMP) method. A dual damascene multi-layer wiring structure can be formed through the above-described steps.
Furthermore, for example, a SiC film 69 is deposited as an antioxidative layer on the dual damascene wiring 68 in the same manner as the lower Cu buried wiring 54.
The application of the above-described conventional dual damascene process to multi-layer wiring after the 0.1 μm generation of micro devices has the following problem.
Since the second mask 59′ is used for forming the connecting holes 63 by etching the SiOC film (MSQ film) 56 used as a connecting hole interlayer film, and for forming the wiring pattern 64 in the wiring groove formation region of the SiO2 film 58, the second mask 59′ requires a certain thickness. For example, when the SiOC film 56 functioning as the connecting hole interlayer film and having a thickness of 400 nm is etched by using the SiN film 59 as the second mask 59′, from the viewpoint of etching electivity, the SiN film 59 having a thickness of 100 nm to 150 nm is required for suppressing widening of the upper portions or scraping of the shoulders of the wiring grooves.
However, when the second mask forming layer, i.e., the SiN film 59, becomes thick, the second mask 59′ is inevitably formed on steps by etching the SiN film 59, thereby causing difficulties in accurately forming a micro pattern of the second mask 59′ on the steps.
The inventor proposes a dual damascene process using three-layer masks in Japanese Unexamined Patent Application Publication No. 2002-221069 in which a SiO2 film of 150 nm in thickness used as a first mask forming layer, a silicon nitride (SiN) film of 100 nm in thickness used as a second mask forming layer, and a SiO2 film of 50 nm in thickness used as a third mask forming layer are deposited on the PAE film 57.
The dual damascene process using the three-layer mask structure proposed in Japanese Unexamined Patent Application Publication No. 2002-221069 (referred to as “prior application” hereinafter) will be described below with reference to FIGS. 14 and 15. FIGS. 14A to 14C and FIGS. 15D to 15F are sectional views showing respective steps for forming a dual damascene structure by the method disclosed in the prior application. In FIGS. 14 and 15, the same portions as those shown in FIGS. 11 to 13 are denoted by the same reference numerals.
First, as shown in FIG. 14A, a laminated film including an organic insulating film 52 and a silicon oxide (SiO2) film 53 is deposited as an inter-wiring insulating film on an underlying insulating film 51 by the same method as in the above-described publication, and then copper (Cu) film buried wiring 54 is formed in the inter-wiring insulating film. Then, a silicon carbide (SiC) film 55, a carbon-containing silicon oxide (SiOC) film 56, and a PAE film 57 are successively deposited on the Cu buried wiring 54.
Then, a SiO2 film 58 of 150 nm in thickness used as a first mask forming layer, a silicon nitride (SiN) film 59 of 100 nm in thickness used as a second mask forming layer, and a SiO2 film 70 of 50 nm in thickness used as a third mask forming layer are successively deposited on the PAE film 57.
Next, a resist mask 60 having a wiring groove pattern as a resist pattern is formed on the SiO2 film 70.
Next, as shown in FIG. 14B, the SiO2 film 70 used as the third mask forming layer is etched through the resist mask 60 by a dry etching method to form a third mask 70′ having a wiring groove intermediate pattern.
Then, as shown in FIG. 14B, a resist mask 61 having a connecting hole pattern is formed on the remaining SiO2 film 70 and SiN film 59 so that at least a portion of the connecting hole pattern overlaps with the third mask 70′ (SiO2 film 70) having the wiring groove intermediate pattern.
Next, the SiO2 film 70 remaining in the connecting hole formation region, the SiN film 59 functioning as the second mask forming layer, and the SiO2 film 58 functioning as the first mask forming layer are etched by a dry etching method using the resist mask 61 having the connecting hole pattern. Then, as shown in FIG. 14C, the PAE film 57 is etched by using the remaining SiN film 59 as a second mask 59′ to form connecting holes 62 for exposing the SiOC film 56. The remaining SiO2 film 70 constitutes the third mask 70′ having a wiring groove pattern.
The resist mask 61 can be removed at the same time as etching of the PAE film 57.
Next, as shown in FIG. 15D, the SiN film 59 is etched by a dry etching method using the third mask 70′ (SiO2 film 70) having the wiring groove pattern to form the second mask 59′ having a wiring groove pattern 64. At the same time, the SiOC film 56 is etched to an intermediate portion to form connecting holes 71.
Next, as shown in FIG. 15E, the lower portion of the SiOC film 56 is etched by using the first mask 58′ comprising the SiO2 film 58 as a mask to form connecting holes 63 for exposing the SiC film 55.
At the same time, the SiO2 film 58 remaining in the wiring groove region is removed by using the second mask 59′ comprising the SiN film 59 having the wiring groove pattern to form the first mask 58′ having the wiring groove pattern.
Next, as shown in FIG. 15F, the PAE film 57 remaining at the bottoms of the wiring grooves is etched by using the first mask 58′ (SiO2 film 58) to form wiring grooves 66, and the SiC film 55 remaining at the bottoms of the connecting holes is etched to form connecting holes 65 communicating with the Cu buried layer 54, thereby completing the predetermined dual damascene process.
Then, the same process as the above-described conventional method is performed to form upper buried wiring 68.
In the dual damascene structure multilayer wiring formed as described above, when the resist mask 61 having the connecting hole pattern is formed, the step difference of the under layer can be suppressed to about 50 nm equal to the thickness of the remaining SiO2 film 70, and thus the resist mask having the high-precision connecting hole pattern can be formed. By using the resist pattern having the high-precision connecting hole pattern, the connecting holes having micro dimensions can be stably formed without deteriorating the shape of the wiring grooves.
Therefore, excellent via contact characteristics can be obtained. By applying the method of this embodiment, a semiconductor device comprising a low dielectric constant interlayer insulating film having a dual damascene structure with a good wiring shape can be manufactured in high yield.
In order to decrease the inter-wiring capacity, the inventor further attempted to use a carbon-containing silicon oxide film (SiOC: relative dielectric constant 3.0) instead of the SiO2 film 53 (relative dielectric constant 4.1) deposited on the organic insulating film 52 and constituting the inter-wiring insulating film of the lower wiring, and the SiO2 film 58 (relative dielectric constant 4.1) constituting the inter-wiring insulating film of the upper wiring and functioning as the first mask forming layer.
The configuration and problem of a modification attempted by the inventor will be described below with reference to FIGS. 16 to 20. FIGS. 16A and 16B, FIGS. 17C and 17D, FIGS. 18E and 18F, FIGS. 19G and 19H, and FIGS. 20I and 20J are sectional views showing the respective steps of the modification. In FIGS. 16 to 20, the same portions as those shown in FIGS. 1 to 10 are denoted by the same reference numerals.
As shown in FIG. 16A, a laminated insulating film including an organic insulating film, for example, a PAE film 2, and a carbon-containing silicon oxide (SiOC) film 3 having a relative dielectric constant of about 3.0 is first deposited on an underlying insulating film 1 deposited on a substrate not shown in the drawing. Then, wiring grooves are formed in the laminated insulating film, and copper (Cu) film buried wiring 4 is formed in the wiring grooves. The SiOC film 3 is deposited by a parallel plate plasma CVD apparatus using methylsilane as a silicon source of raw material gases.
Then, a silicon carbide (SiC) film 5 functioning as an antioxidative layer for the Cu film, a carbon-containing silicon oxide (SiOC) film 6 and a polyaryl ether (PAE) film 7 as an organic insulating film are successively deposited on the Cu-buried wiring 4.
Then, a SiOC film 8 having a relative dielectric constant of about 3.0 and functioning as a first mask forming layer, a silicon nitride (SiN) film 9 functioning as a second mask forming layer, and a SiO2 film 10 functioning as a third mask forming layer and having a thickness of 50 nm are successively deposited on the PAE film 7.
Then, a resist mask 11 having a wiring groove pattern as a resist pattern is formed on the SiO2 film 10.
Next, as shown in FIG. 16B, the SiO2 film 10 functioning as the third mask forming layer is etched by dry etching through the resist mask 11 to form a third mask 10′ having a wiring groove pattern 13 on the SiN film 9.
After etching of the SiO2 film 10, the resist mask 11 and the extraneous matters remaining after etching are completely removed by an appropriate post-treatment.
Then, as shown in FIG. 17C, a resist mask 12 having a connecting hole pattern is formed on the remaining SiO2 film 10 and SiN film 9 so that at least a portion of the connecting hole pattern overlaps with the third mask 10′ (SiO2 film 10) having the wiring groove pattern 13.
Then, the third mask 10′ (SiO2 film 10), the SiN film 9 functioning as the second mask forming layer, and the SiOC film 8 functioning as the first mask forming layer are etched by dry etching through the resist mask 12, and the PAE film 7 is further etched by using the remaining SiN film 9 as a second mask to form connecting holes 14 for exposing the SiOC film 6, as shown in FIG. 17D. The remaining SiO2 film 10 forms the mask 10′ having the wiring groove pattern 13.
The resist mask 12 can be removed at the same time as etching of the PAE film 7.
Next, as shown in FIG. 18E, the SiN film 9 is etched by a dry etching method using the third mask 10′ (SiO2 film 10) having the wiring groove pattern 13 to form the second mask 9′ having a wiring groove pattern 15.
In the step of etching the SiN film 9 functioning as the second mask forming layer through the third mask 10′, the SiOC film 6 exposed at the bottoms of the connecting holes 14 is etched to an intermediate position to dig down the connecting holes 14 and form connecting holes 16.
Under these etching conditions, the etching selectivity (SiN/SiOC) to the SiOC film can be set to be slightly smaller than 1, and thus when the SiN film 9 of 100 nm in thickness is etched, the connecting holes 16 can be dug down in the SiOC film 6 to a depth of 150 to 200 nm including a necessary amount of over etching.
Next, the remaining lower layer of the SiOC film 6 is etched by using a first mask 8′ (SiO2 film 8) as a mask to form connecting holes 17 for exposing the SiC film 5, as shown in FIG. 18F. At the same time, the first mask 8′ (SiOC film 8) remaining in the wiring groove region is removed by using the second mask 9′ (SiN film 9) having the wiring grove pattern 15 to form the apertures 18 of wiring grooves.
However, as shown in FIG. 19G, it was confirmed that a region 19 including the remaining SiOC film 8 occurs in the aperture 18A of a wide wiring groove during the formation of the connecting holes 17 and the wiring grooves 18.
This is a phenomenon characteristic of etching of the SiOC film 8 based on the processing selectivity of the SiOC film to be processed to the SiN film 9 used as the etching mask. Namely, while the SiOC film 6 in which the connecting holes 17 are formed, and the SiOC film 8 remaining in apertures narrower than a certain wiring groove can be easily removed to form apertures, carbon is excessively supplied from the SiOC film 8 into the etching atmosphere in such an aperture of a wide wiring groove as the aperture 18A to possibly stop etching of the SiOC film.
It was also found that when the etching conditions are changed for preventing the phenomenon and easily forming the apertures in the SiOC film, the selectivity to the SiN film used as the etching mask is decreased to increase a conversion difference. The “conversion difference” means a difference between the open dimension of the first mask 8′ (SiOC film 8) and the open dimension of the second mask 9′ (SiN film 9).
Then, the PAE film 7 remaining at the bottoms of the wiring grooves 18 is etched to form wiring grooves 20, and the SiC film 5 exposed at the bottoms of the connecting holes 17 is etched to complete the predetermined dual damascene process.
The second mask 9′ (SiN film 9) remaining outside the wiring groove region is removed at the same time as etching of the SiC film 5 exposed at the bottoms of the connecting holes 17.
However, etching of the PAE film 7 and the SiC film 5 has the problem of causing three problems with the shape.
The first problem is that the aperture pattern for a wide wiring groove has the region 19 in which the SiOC film 8 remains, and thus the wiring groove 20 having a predetermined shape cannot be formed by etching a region 21 of the PAE 7, as shown in FIG. 19H.
The second problem is that misalignment between the connecting holes 17 and the lower wiring 4 causes slit-shaped trenches 22 in the inter-wiring insulating film of the lower wiring 4 immediately below the connecting holes 17.
The third problem is that in the first mask 8′ (SiOC film 8) remaining below the second mask 9′ (SiN film 9), the aperture shoulders of the wiring grooves 20 are significantly scraped off.
The second and third problems are due to the fact that in etching the SiC film 5 and the SiN film 9, only a selectivity (SiC/SiOC or SiN/SiOC) of about 1 to the SiOC film 8 can be secured.
Then, the extraneous materials remaining after etching on the wide walls of the wiring grooves 20 and the connecting holes 17, and Cu altered layers at the bottoms of the connecting holes 17 are cleaned off by a post-treatment with a chemical and hydrogen annealing. Then, as shown in FIG. 20I, for example, a Ta film 23 is deposited as a barrier metal by sputtering, and a Cu film 24 is deposited by electrolytic plating or sputtering to bury a conductive film in the connecting holes 17 and the wiring grooves 20.
However, in a region where misalignment occurs between a connecting hole 17 and the lower wiring 14, the slit-shaped trench 22 is produced to locally increase the aspect ratio, thereby causing the problem of producing a burying defect 25.
Then, as shown in FIG. 20J, in the deposited Ta film 23 and Cu film 24, unnecessary portions for the wiring pattern are removed by a chemical mechanical polishing (CMP) method to form a dual damascene multi-layer wiring structure. Like in the lower wiring pattern, for example, a SiC film 27 is deposited as an antioxidative layer on the dual damascene wiring 23/24.
However, in an aperture 26 for wide wiring, the SiOC film 8 remains in the region 19, and the PAE film 7 remains in the region 21, thereby causing the problem of locally thinning the wiring layer in the aperture 26.
The multi-layer wiring formed by the above-described dual damascene process has the problem of locally increasing the resistance of the connecting holes and wiring due to the occurrence of the burying defect 25 of the Cu film in the connecting holes and the locally thinned region 26 of the wiring film.
Also, the condition of the SiOC film 8 remaining in the region 19 varies. In an extreme case, wide wiring is completely broken, leading to a conduction defect.
Furthermore, even when wiring is electrically connected to the connecting holes within the operation range of a semiconductor device, a current and thermal stress are concentrated in the thin local region of the Cu wiring, and the growth of the burying defect 25 occurring in a connecting hole 17 is highly likely to induce reliability defects such as electromigration and stress migration in the operating environment.